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A.13 *SRE — SERVICE REQUEST ENABLE COMMAND
Syntax:
*SRE<integer>
grammed.
Description: Sets the condition of the Service Request Enable register. The Service Request Enable register
determines which events of the Status Byte Register are summed into the MSS (Master Status Sum-
mary) and RQS (Request for Service) bits. RQS is the service request bit that is cleared by a serial
poll, while MSS is not cleared when read. A "1" (1 = set = enable, 0 = reset = disable) in any Service
Request Enable register bit position enables the corresponding Status Byte bit to set the RQS and
MSS bits. All the enabled Service Request Enable register bits then are logically ORed to cause Bit 6
of the Status Byte Register (MSS/RQS) to be set. Related Commands: *SRE?, *STB?. (See exam-
ple, Figure A-1.)
TABLE A-3. SERVICE REQUEST ENABLE AND STATUS BYTE REGISTER BITS
CONDITION
OPER
BIT
7
VALUE
128
A.14 *SRE? — SERVICE REQUEST ENABLE QUERY
Syntax:
*SRE?
Description: Reads the Service Enable Register. Used to determine which events of the Status Byte Register are
programmed to cause the power supply to generate a service request (1 = set = function enabled, 0 =
reset = function disabled). Related Commands: *SRE, *STB? (See example, Figure A-1.)
A.15 *STB? — STATUS BYTE REGISTER QUERY
Syntax:
*STB?
Description: Reads Status Byte Register without clearing it. This Query reads the Status Byte Register (bit 6 =
MSS) without clearing it (1 = set = function enabled, 0 = reset = function disabled). The register is
cleared only when subsequent action clears all set bits. MSS is set when the power supply has one
ore more reasons for requesting service. (A serial poll also reads the Status Byte Register, except that
bit 6 = RQS, not MSS; and RQS will be reset.) Related Commands: *SRE, *SRE?. (See example, Fig-
ure A-1.)
A.16 *TRG — TRIGGER COMMAND
Syntax:
*TRG
Description: Triggers the power supply to be commanded to preprogrammed values of output current and
voltage. When the trigger is armed, *TRG generates a trigger signal if TRIG:SOUR is set to BUS and
the WTG bit in Status Operational Condition register (bit 5, Table B-3) is asserted. The trigger is armed
by sending a) INIT:CONT ON to continuously arm the trigger and allow subsequent *TRG commands
to generate the trigger signal or b) if INIT:CONT is set to OFF, sending INIT arms the system and
allows a *TRG to generate a single trigger. If *TRG is received while the trigger is not armed, the trig-
ger is not produced and no error is generated.
The trigger will change the output of the power supply to the output voltage and current levels speci-
fied by VOLT:TRIG and CURR:TRIG commands and clear the WTG bit in the Status Operation Condi-
tion register. If INIT:CONT 1 (ON) has been issued, the trigger subsystem is immediately rearmed for
subsequent triggers, and the WTG bit is again set to 1. *TRG or GET are both addressed commands
(only devices selected as listeners will execute the command). If output is set to OFF, *TRG is ignored.
Related Commands: ABOR, INIT, TRIG, CURR:TRIG, VOLT:TRIG. (See example, Figure A-1.
BIT 4886 080709
where <integer> = value from 0 - 255 per Table A-3, except bit 6 cannot be pro-
MSS
ESB
MAV
QUES
RQS
6
5
4
3
64
32
16
8
Response: <integer> = value from 0 - 255 per Table A-3.
Response: <integer> value from 0 to 255 per Table A-3.
BUSY
LIST RUN
ERR
LIST
OPER
BUSY
QUE
RUN
MSS
RQS
2
1
0
ESB
MAV
4
2
1
QUES
ERR QUE
*SRE
Busy
List is running
Operation Status Summary
Master Status Summary
Request for Service
Event Status Byte summary
Message available
QUEStionable Status Summary
1 or more errors occurred (see
PAR. B.130)
*SRE?
*STB?
*TRG
)
A-5
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