Table of Contents
Advertisement
FIGURE 3-20.
STATUS REPORTING STRUCTURE
A zero to one transition of a condition register is added to the event register. Reading an event
register clears all of the bits found in the event register. If any bits are set in an event register,
the following condition register bit is then set. For example, if the STAT:QUES:ENB (enable) reg-
ister has bit 0 set and a voltage error is detected, the event registers bit 0 is set. The 1 in the
event register causes bit 3 of the status byte to be asserted. The Service Request register is
ANDed with its enable register for all bits except bit 6. The result is placed in bit 6 of the Service
Request register. If bit 6 is a 1 (true), it causes the MBT-G power supply to assert the SRQ line
to the host controller.
3-61
BOP HIPWR 080709
Advertisement
Table of Contents
