Itanium ® 2 Processor System Bus Clock And Processor Clocking; Processor Full, Normal And Low Power Mode With Timings; Processor Power States - Intel Itanium 2 Processor Datasheet

Electrical Specifications
Table 2-24. Processor Power States
Zero to 1st Power State (A)
1st Power State to 2nd Power State (B)
2nd Power State to 3rd Power State (C) 10 μs
3rd Power State to 2nd Power State (D) 10 μs
2nd Power State to 1st Power State (E)
Normal Operating Range (F)
Thermal Trip (G)
Figure 2-5. Processor Full, Normal and Low Power Mode with Timings
2.7 Itanium
Processor Clocking
The BCLKn and BCLKp inputs control the operating frequency of the Itanium 2 processor system
bus interface. All Itanium 2 processor system bus timing parameters are specified with respect to
the falling edge of BCLKn and rising edge of BCLKp. The Itanium 2 processor core to bus ratio
must be configured during system reset by using the A[21:17]# pins (see
these pins during the system reset sequence determines the multiplier that the PLL will use for the
internal core clock. Because the A[21:17]# signals pins have different uses after a system reset is
complete, these signals must be multiplexed for configuration during reset and for normal use after
reset. See the Intel
information on Itanium 2 processor system bus clock and processor clocking.
32
State Transition
Current Level
B
100A
75A
40A
5A
C
0A
A
®
2 Processor System Bus Clock and
® ®
Itanium 2 Processor Hardware Developer's Manual for complete
Ramp Rate
10 μs
Off state to initial power on.
10 μs
1st power state is defined as the system
minimum operating load. Fastest power up
sequence.
2nd power state is defined as 75% of full
power.
3rd power state is defined as 40% of full
power.
10 μs
Typical fast power down to initial power on.
100 A/μs max Defined as 75% to 100% of full power.
1ns ±250 ps or one Processor over temperature condition
processor core cycle. emergency shutdown.
D
F
E
Comment
Current Level
100A
75A
F
40A
5A
0A
G
000672b
Table 2-25). The value on
Datasheet