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Testing Performance
To test the single-clock, multiple-edge, state acquisition (logic analyzer)
7 Test the next setup/hold combination.
a In the logic analyzer Format menu, select Master Clock.
b Turn off and disconnect the c!ockjust tested
c Repeat steps 1 through 6 for the next setup/hold combination listed in step 1 on
page 3-54, until all listed setup/hold combinations have been tested.
When aligning the data and clock waveforms using the oscilloscope, align the waveforms
according to the setup time of the setup/hold combination being tested, +0.0 ps or -100 ps.
Test the next channels
• Connect the next combination of data channels and clock channels, then test them.
Start on page 3-52, "Connect the logic analyzer," connect the next combination, then continue
through the complete test.
3-59
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