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Testing Performance
To test the multiple-clock. multiple-edge. state acquisition (logic analyzer)
8 Using the Delay mode of the pulse generator channell, position the pulses
according to setup time of the setup/hold combination selected,
+0.0
ps or
-100
ps.
a On the Oscilloscope, select [Define meas] Define
LI.
Time - Stop edge: falling.
b On the oscilloscope, select [Shift]- width: channel 2, then select [Enter] to verify the
clock signal pulse width (- width (2)). If the pulse width is outside the limits, adjust the
pulse generator channel I width until the clock pulse width is 3.500 ns, +0 ps or
-lOOps.
c On the oscilloscope, select [Shift]
LI.
Time. Select Start src: channell, then select
[Enter] to display the setup time
(LI.
Time (1)-(2)).
d Adjust the pulse generator channel 1 Delay until the pulses are aligned according the
the setup time of the setupihold combination selected, +0.0 ps or -100 ps.
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L______
16555W06
9 Select the clocks to be tested.
a Select the clock field to be tested, then select the clock edges as indicated in the table.
The first time through this test, use the top clocks and edges (HP l660ElESIEP and
liP 166lElESIEP).
Clocks
HP 1660E/ES/EP and HP 1661E/ES/EP
JJ.+ MJ.+ NJ.
KJ.+ LJ.+ pJ.
HP 1662E/ESjEP and HP 1663E/ESjEP
JJ. +KJ. +LJ. + MJ.
b Select Done to exit the Master Clock menu.
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1
•
3-47
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