HP 1660E Series Service Manual page 57

Testing Performance
To testthe single-clock, single-edge, state acquisition (logic analyzer)
Check the setup/hold combination
1 Select the logic analyzer setup/hold time.
a In the logic analyzer Format menu, select Master Clock.
b Select the SetuplHold field, then select the setup/hold combination to be tested for all
pods. The first time through this test, use the top combination in the following table.
Setup/Hold Combinations
3.5/0.0 ns
0.0/3.5 ns
c Select Done to exit the setup/hold combinations.
POd5 A7,AS
~.5JOO
ns)
~
EJ
on",
Done
S>etvp/HoiO
11il~ler Clocl
pod~ A~.A4 POd5 Al ,A:::
I
0.",.0,,,1
I
'."'.0
",I
0.513.0
ns
0.0/3.5
n$
1.012.S 05
(~t
rormot
tlACHIUE I )
lllontiode
J_
MemOn1/100rlH3
3-31