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Theory of Operation
Pattern Generator tests (Patt Gen)
Subtest #3 - If Instruction Test This test checks the functionality of the if branching.
Instruction memory is loaded with a wait on event 'a' instruction in the non-if branch of
memory and a break instruction in the if branch.
The first pass of the test sets the branch pattern to a never branch condition. The board is
started and a wait is begun for the vectors to get to the wait instruction. The hardware
should stop on the wait instruction, not the break. The main status is checked to verify
this stop condition.
The second pass of the test sets the branch pattern to always branch.
Again
the board is
started and a wait is begun. In this case the break instruction should be the stop condition.
Diagnostic Integer Value: The integer returned will have the following bit format:
BIT#:
115,14,13,12,11,10,9,8,7,6,5,4
13,2'1,0
unused
Test Mode
The Test Mode bit positions have the following meaning:
o
-passed
1 - failed to stop on wait in non-if branch
2 - took
if
branch on no branch event
4 - failed to stop on break in if branch
8 - took non-if branch on any branch event
Output Patterns for testing with an external logic analyzer or oscilloscope
The performance test will set up two predefined patterns for examining the board from an
external analyzer or scope. This allows the user to check the output pipeline for functionality
and also helps to perform a quick check of all bit locations in the data VRAMS.
The data is output based on the frequency mode chosen by the user:
50MHz Mode - 20 ns period
100MI-Iz Mode - IOns period
200MHz Mode -
5 ns period
Either a checkerboard pattern (alternating Is and Os across the output channels) or a walking
ones pattern are available.
8-26
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