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Testing Performance
To
test the single-clock, multiple-edge, state acquisition (logic analyzer)
Check the setup/hold with single clock, multiple clock edges
1 Select the logic analyzer setup/hold time.
a In the logic analyzer Format menu, select Master Clock.
b Select and activate any multiple clock edge.
c Select the SetuplHold field, then select the setup/hoid to be tested for all pods. The
first time through this test, use the top combination in the following table.
Setup/Hold Combinations
4.0/0.0 ns
0.0/4.0 ns
d Select Done to exit the setup/hold combinations.
pods ALA:!
( -1.0/0.0
os]
r1i>ster ClOCk
Setup/HO 1d
pod~
113.A4
( 4.0/('.0
os]
:::'0/2.0
os
1.5/2.51>5
pods A7,';6
( 4.0/0.0
os)
~
1.0/3.0 05
8 ' "
Done
0.5/3.5 05
2 Using the Delay mode of the pulse generator channell, position the pulses
according to the setup time of the setup/hold combination selected, +0.0 ps or
-lOOps.
a On the Oscilloscope, select [Define meas] Define
/1
Time - Stop edge: rising.
b In the oscilloscope timebase menu, select Position. Using the oscilloscope knob,
position the faliing edge of the data waveform so that it
is
centered on the display.
c
On
the oscilloscope, select [Shift]
/1
Time. Select Start src: channell, then select
[Enter] to display the setup time
(/1
Time(1)-(2)).
3-56
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