HP 1660E Series Service Manual page 228

1
5,4,3,2, 1,0
Failed RAM
Theory of Operation
Pattern Generator tests (Patt Geu)
Bits 6-13 contain the row of the page that failed.
Bits 0-5 contain the failure code for the six RAM ICs on the board. Bits 0-4 contain the failure
code for the RAMs for pod 1-5, and bit 5 contains the failure code for the RAM used for
instructions. A one in the bit position indicates that that RAM provided incorrect infonnation.
Address Counter Test
The Address Counter Test contains four subtests that check the functionality of the column
and row address counters for board RAM. The four subtests use each of the four loop registers
to perfonn the test.
The first step of the test is to load memory using the current loop register with a specific
pattern for the address counter. Memory is loaded with OxOOOO except at predetermined RAM
row and column positions, which are loaded with OxFFFF.
The current loop register is used to set the address for the OxFFFF loading. The loop register
is also used to reset the addresses back to zero for starting the stepping process.
After memory has been loaded the clock is stepped through
all
possible RAM addresses
checking for the correct data at each address.
Passing the Address Counter Test implies that each RAM memory location can be accessed by
the RAM addressing circuitry while under control of the clocking circuit. Passing the test also
implies that the loop registers are operating correctly.
Diagnostic Integer Valne: This test checks the counters of the entire board. The
returned integer has the following format:
81T#:
115 114,13,12,11,10,9,8,7,6
Row/Col Fail row
Bit 15 is used to flag where the value of the fail row bits (6-14) came from. If the failing row
value was less than 511 bit 15 is set to zero. If the failing row was greater than 511 bit 15 is set
to one. The failed row bits (6-14) contain a value from 0 to 255.
Bits 0-5 contain the failure code for the six RAMs on the board. Bits 0-4 contain the failure
code for the RAM for pods 1-5, and bit 5 contains the failure code for the RAM used for
instructions. A one in the bit position indicates that that ram provided incorrect infonnation.
Instrnction Tests
This test contains three subtests that have unique descriptions. Each subtest is described
below.
Passing the Instruction Tests implies that CPU addressing, RAM addressing, and the
instruction decoder of the board responds properly to user commands.
Subtest #1- Instruction Interface Test This test checks the functionality of the
break command in the instruction memory and the status register that reads the break.
On the first pass of this test, instruction memory is loaded with zeros (NOP). The board is
run and the main status register polled to see that the hardware is
running. If
the
hardware is stopped the test fails.
The second pass of the test places the break instruction on the next to last vector in
memory. Again the hardware is started and the status is read. This time the board should
stop or the test fails.
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