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Theory of Operation
The Logic Acquisition Board
Logic Acquisition Board Theory
Probing
The probing circuit includes the probe cable and terminations. The probe cable consists of
two l7-channel pods which are connected to the circuit board using a high-density connector.
Sixteen single-ended data channels and one single-ended clock/data channel are passed to the
circuit board per pod.
1£ the clock/data channel is not used as a state clock in state acquisition mode, it is available as
a data channel. The clock/data channel is also available as a data channel in timing acquisition
mode. Eight
(HP
l660E/ESIEP), six (HP l661EIESIEP), four (HP l662EIESIEP), or two
(l663EIESIEP) clock/data channels are available as data channels, however only six
clock/data channels can be assigned as clock channels in the HP 1660ElESIEP and
HP l661E/ESIEP. All clock data channels available in the HP l662ElESIEP and
HP l663ElESIEP can be assigned as clock channels.
The cables use nichrome wire woven in polyarmid yarn for reliability and durability. The pods
also include one ground path per channel in addition to a pod ground. The channel grounds
are configured such that their electrical distance is the same as the electrical distance of the
channel.
The probe tip assemblies and termination modules connected at the end of the probe cables
have a divide-by-lO RC network that reduces the amplitude of the data signals as seen by the
circuit board. This adds flexibility to the types of signals the circuit board can read in addition
to improving signal integrity.
The terminations on the circuit board are resistive terminations that reduce transmission line
effects on the cable. The terminations also improve signal integrity to the comparators by
matching the impedance of the probe cable channels with the impedance of the signal paths of
the circuit board. All 17 channels of each pod are terminated in the same way. The signals
are reduced by a factor of 10.
Comparators
Two proprietary 9-channel comparators per pod interpret the incoming data and clock signals
as either high or low depending on where the user-programmable threshold is set. The
threshold voltage of each pod is individually programmed, and the voltage selected applies to
the clock channel as well as the data channels of each pod.
Each of the comparator ICs has a serial test input port used for testing purposes. A test bit
pattern is sent from the Test and Clock Synchronization Circuit to the comparator. The
comparators then propagate the test signal on each of the nine channels of the comparator.
Consequently, all data and clock channel pipelines on the circuit board can be tested by the
operating system software from the comparator.
Acqnisition
The acquisition circuit is made up of a single HP proprietary ASIC. Each ASIC is a 34-channel
state/timing analyzer, and one such ASIC is included for every two logic analyzer pods. All of
the sequencing, pattern/range recognition, and event counting functions are performed on
board the IC.
In
addition to the storage qualification and counting functions, the acquisition ASICs also
perform master clocking functions. All six state acquisition clocks are fed to each IC, and the
lCs generate their own sample clocks. Every time you select RUN, the ICs individually
perform a clock optimization before data is stored.
8-8
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