Check The Setup/Hold With Single Clock Edges, Multiple Clocks - HP 1660E Series Service Manual

Testing Performance
To test the multiple-clock. multiple-edge. state acquisition (logic analyzer)
Check the setup/hold with single clock edges, multiple clocks
1 Select the logic analyzer setuplhold time.
a
In the logic analyzer Format menu, select Master Clock.
b Select and activate any two clock edges.
c Select the SetuplHold field and select the setup/hold to be tested for all pods. The first
time through
this
test, use the top combination in the following table.
Setup/Hold Combinations
4.5/0.0 ns
0.0/4.5 ns
d Select Done to exit the setup/hold combinations.
pods AI,AZ
( 4.5/0.0 liS]
pods A7,Ae
{ .. 1 ,5/0,0
ns]
pods 113,A4
I
-1,5/0.0
n~]
2.012.5
nS
(Analy~er J( form~t
J1ACHWE 1 )
(1,5/4.0
n~
: _
1.513.0 flS
8 """
Done
I Jl(:>.5 flS
2 Disable the pulse generator channell COMP (with the LED off).
3 Using the Delay mode of the pulse generator channell, position the pulses
according to the setup time of the setuplhold combination selected,
+0.0
ps or
-100
ps.
a On the Oscilloscope, select [Derme meas
1
Define Ll TIme - Stop edge: rising.
b In the oscilloscope timebase menu, select Position. Using the oscilloscope knob,
position the rising edge of the clock waveform so that it is centered on the display.
c On the oscilloscope, select [Shift] Ll TIme, then select [Enter] to display the setup time
(Ll Time(l)-(2)).
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