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Testing Performance
To teslthe single-clock, single-edge, state acquisition (logic analyzer)
2 Set up the Format menu.
a Press the Format key. Select State Acquisition Mode, then select
Full
Channel/4K
Memory/IOOMHz.
b Select the field to the right of each pod, then select ECL
in
tlle pop-up menu. Use the
knob to access pods not shown on the screen.
( Annl\lZ8r )(
Formol
tJACHWE 1
)
15
.. 87
15 . , 87.
,0
LM.I
Ell
lI.,b2
L<lbJ
L"b~
LObS
Lobo
LOb?
Lbb8
··11················11·
····1
3 Set up the Trigger menu.
a Press the Trigger key. Select Modify Trigger, select Clear Trigger, then select All
in
the pop-up menu.
b Select Count
Off.
Press Select again, then select Time
in
the pop-up menu. Select
Done to exit the menu.
HP 1662E1ESlEP - "OOAA"
HP 1663E1ESlEP - "OOOA"
c Select the field labeled I under the State Sequence Levels. Select the field labeled
"anystate," then select "no state." Select Done to exit the State Sequence Levels menu.
d Select the field next to "a," under the label Lab 1. Type tlle following for your logic
analyzer, then press the Select key.
HP 1660ElESIEP - "OOAA"
HP 166lElESlEP - "OO2A"
MAC HE
Anlll yzer
Trtgger
,
;
,
Print
'""
Stole Sequence Levels
Timer
ArffiU'9
,
,
Q
Hhlle stonng
~no
stele"
- -
Con Iro I
TRIGGER On
"/)"
,
time
AcqU!Sl tlon
Store "anyctole"
- -
Control
0
(
Count
I
TIme
Modlly
Trigger
+Lnbel+
~
.. re1' m s ..
~
,
-
,
~
,
~
~~
3-26
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