HP 1660E Series Service Manual page 56

Testing Performance
To test the single-clock. single-edge. state acquisition (logic analyzer)
OAT A SIGNAL
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I-+-+-+--
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[LJOCK SIGNAL ,
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'_,- - Clock Period
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1655SW02
3 Check the data pulse width. Using the oscilloscope, verify that the data pulse width
is 3.500
ns,
+0 ps or -100 ps.
a On the Oscilloscope, select [Define meas] Define
/!,.
Time - Stop edge: rising.
b In the oscilloscope timebase menu, select Position. Using the oscilloscope !mob,
position the rising edge of the clock waveform so that it
is
centered on the display.
c On the oscilloscope, select [Shift] + width: channe 11, then select [Enter] to display
the data signal pulse width (+width (1)).
d If the pulse width
is
outside the limits, adjust the pulse generator channel
2
width until
the pulse width
is
within limits.
DATA SIGNAL
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l..-Dolo Pulse
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[LOCK SIGNAL I
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1655SWO
3-30