HP 1660E Series Service Manual page 169

Troubleshooting
To testthe logic analyzer probe cables
4 Set up the Format menu.
a Press the Format key.
b Move the cursor to the field showing the channel assignments for the pod 1lllder test.
Press the Clear
Entry
key 1llltil the pod channels are all assigned Call asterIsks C*)).
Press the Done key.
( AnolFer )( Format MI'ICHWE I
~~
Siote AcqUISItion MO<le (Symn01S
I
<':;'"~'~'~C~"~'"~"~'~"r':'~"~'"~'~':"'~'~OC~"~"~'l:~~~~$q
CloCI. Inputs Pod
fi::
TTL
~
TTL
Moster CloCI NostH Clocl
Lllbt
EI
Lob;:
Leb:>
LII04
LubS
LabD
LIlb7
Lab8
c Select Master Clock, then select a double edge for the clock ofthe pod 1lllder test.
Tum off the other clocks.
( AnOly;:er)(
Format tlAClHNE 1
Slole AcqUISitIon MOde
~
Full ChonnelJ-lK Memory/lC'OnH2 ~
noster
ClOCk
QUALS'
Ol~
@ ) 0 2 C E J
03~ 8D..l~
( S,,!upfHOld
d In the Master Clock menu, select SetuplHold, then select 4.0/0.0 ns for the pod being
tested. Select Done. Select Done again to exit the Master Clock menu.
~(
Formal
Stote ACqulS) lIon Mode
FUll CMmwl/-lr t1emOr;l/lOOMH:
EDGES'
DUALS'
1.5/;:.5 n5
Off
1.0/3.0 05
0.51:;.5
os
B ' " "
Done
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