HP 1660E Series Service Manual page 84

Logic analyzers
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Testing Performance
To test the single-clock, multiple-edge, state acquisition (logic analyzer)
4 If you have not already created a Compare fIle for the previous test (single-clock,
single-edge state acquisition, page 32), use the following steps to create one. For
subsequent passes through this test, skip this step and go to step 5.
a Press Run. The display should show an alternating pattern of"AA" and "55". Verify the
pattern by scrolling through the display.
b Press the List key. In the pop up menu, use the RPG lmob to move the cursor to
Compare. Press Select.
c In the Compare menu, move the cursor
to
Copy Listing
to
Reference, then press the
Selectkey.
d Move the cursor to Specify Stop Measurement and press the Select key. Press Select
again to
turn
on Compare. At the pop up menu, select Compare. Move the cursor to
the Equal field and press the Select key. At the pop up menu, select Not Equal. Press
Done.
e Move the cursor to the Reference Listing field and select. The field should toggle to
Difference Listing.
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5 5
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<15
Ali
6
n~
55
16
r\~
All
B
n$
55
e
ns
All
6
ns
55
16 liS
All
B
ns
S5
8
n~
All
8
n~
55
16
ns
AA
e ns
55
0
n~
AR
8 nS
55
16 ns
I)
Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained
without the "Stop Condition Satisfied" message appearing, then the test passes.
Press Stop to halt the acquisition. Record the Pass or Fail results in the
perfonnance test record.
6 Test the next clock.
a Press the Format key, then select Master Clock.
b Tum off and disconnect the clock
just
tested.
c Repeat steps 4, 6 and 7 for the next clock listed
in
the table
in
step 4, until
all
clocks
have been tested.
3-58

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