HP 1660E Series Service Manual page 125

Logic analyzers
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Performance Test Record (continued)
Testing Performance
Performance Test Record (logic analyzer)
Test
Settings
Results
Multiple-Clock,
Enable pulse generator, channel 2
Disable pulse generator, channel 2
Multiple-Edge
COMP (LED on)
CDMP (LED off)
Acquisition
Pass/Fail
Pass/Fail
All Pods, Channel 3 Setup/Hold Time
4.5/0.0 ns
JI
+
MI
+
NI
JJ.+ MJ. + NJ.
KI + LI + PI
KJ.+LJ.+PJ.
Setup/Hold Time
0.0/4.5 ns
JI
+
MI + NI
JJ.+MJ.+NJ.
KI + LI
+
PI
KJ. + LJ. + pJ.
All Pods, Channel
Setup/Hold Time
4.5/0.0 ns
JI + MI + NI
JJ.+ MJ.+ NJ.
11
KI
+
LI +PI
KJ. + LJ. +pJ.
SetuplHold Time
0.0/4.5 ns
JI + MI + NI
JJ.+MJ.+NJ.
KI + LI + PI
KJ.+LJ.+PJ.
3-99

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