Verify The Test Signal - HP 1660E Series Service Manual

Logic analyzers
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Testing Performance
To test the multiple-clock, multiple-edge. state acquisition (logic analyzer)
Verify the test signal
1 Check the clock pulse width. Using the oscilloscope, verify that the clock pulse
width is 3.500 ns, +0 ps or -100 ps.
a Enable the pulse generator channell, channel 2, and trigger outputs (LED off).
b In the oscilloscope Timebase menu, select Scale: 1.000 nsldiv.
c In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob,
position the clock waveform so that the waveform
is
centered on the screen.
d On the oscilloscope, select [Shift]
+
width: channel 2, then select [Enter] to display the
clock signal pulse width
(+
width (2)).
e
If
the pulse width
is
outside the
limits,
adjust the pulse generator channell width until
the pulse width
is
within
limits.
OAT II SIGNAL
I
I
I
I
~~
H-I-r:
-t-t-H++-t
+-H-f-j~+-+-I-l-+-f-+-t-+-+-H-l-
I
r
CLOCK SIGNAL
l-l
I
~
I I
I
-1-1-)-+-1-I-j
r-t-t-t-j-I-t-t-t-
Clock Pulse
Wldlh
·-1
16555W1
2 Check the clock period. Using the oscilloscope, verify that the clock period is
10.000 ns, +0 ps or -250 ps.
a In the oscilloscope Timebase menu, select Scale: 2.000 nsldiv.
b In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob,
position the clock waveform so that a rising edge appears at the left of the display.
c
On
the oscilloscope, select [Shift] Period: channel 2, then select [Enter] to display the
clock period (period(2)). If the period
is
not less than 10.000
TIS,
go to step d. If the
period
is
less than 10.000
TIS,
go to step 3.
d In the oscilloscope Timebase menu, increase Position 10.000
TIS.
If
the period
is
not
less than 10.000 ns, decrease the pulse generator Period in 10 ps increments until one
of the two periods measured
is
less than 10.000
TIS.
3-42

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