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Testing Performance
To test the multiple-clock. multiple-edge. state acquisition (logic analyzer)
d Adjust the pulse generator charmell Delay until the pulses are aligned according the
the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.
OAT
A
SIGNIIL
l~
I
I
=+~"
...
I
~
I
1-1-+-+-_ _
1-1
I
I----Setup Tirne
~:~
I
(LOCK SIGNAL
I:
I
II
=tj
.-H..-j~---H-+-t-+++-t-t-j-l-l
1
I
!
I
II
I
1655SW09
4 Select the clocks to be tested.
a Select the clock field to be tested and then select the clock edges as indicated in the
table. The
first
time through
this
test, use the top clocks and edges (HP 1660ElESlEP
and HP l661ElESlEP). Note that the clocks used depends on which logic analyzer
you have.
Clocks
HP 1660EjESjEP and HP 1661EjESjEP
JI + MI + NI
KI+ LI+ PI
HP 1662EjES/EP and HP 1663E/ES/EP
JI + KI + LI + MI
b Corrnect the rising edge clocks to the pulse generator charmell output.
c Select Done to exit the Master Clock menu.
~ (
FormH
I1"CHWE
1
)
Sl~le
Acqul:;1110n Moae
~
Full Chonnel/2K Memoru/l00l1H: ~
Mllster Clocl:
JT+fll+Nr
DUALS'
Ol~
802~ 03~ 80-1~
L
t
SetuplHold
l
•
3-45
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