HP 1660E Series Service Manual page 50

To test the single-clock, single-edge, state acquisition
(logic analyzer)
Testing the single-clock, single-edge, state acquisition verifies the performance of the
following specifications:
• Minimum master-to-master clock time
• Maximum state acquisition speed
• SetuplHold time for single-clock, single-edge, state acquisition
• Minimum clock pulse width
This test checks two combinations of data channels using a single-edge clock at two
selected setup/hold times.
Equipment Required
Equipment
Pulse Generator
Digitizing Oscilloscope
Adapter
SMA Coax Cable
(Qty
31
Coupler
BNC Test Connector,
6x2
(Qty
41
Critical Specifications
100 MHz 3.5 ns pulse width, < 600 ps rise time
;" 6 GHz bandwidth, < 58 ps rise time
SMA(m)-BNC(fl
18 GHz bandwidth
BNC(m)(ml
Recommended Model/part
HP 8133A option 003
HP 54750A, with HP 54751A
plugin
HP 1250-1200
HP8120-4948
HP1250-0216
Set up the equipment
1 Tum on the equipment required and the logic analyzer. Let them warm up for
30 minutes before beginning the test
if
you have not already done so.
2 Set up the pulse generator.
a Set up tile pulse generator according to tile following table.
Pulse Generator Setup
Timebase
Mode: Int
Period: 10.000 ns
Channel 2
Mode: Pulse
Divide: PULSE
+
2
Width: 3.500 ns
High: -0.90 V
Low: -1.70 V
Period
Divide: Divide
+
2
Ampl: 0.50 V
Dffs: 0.00 V
Channell
Mode: Pulse
Delay: 0.000 ns
Width: 3.500 ns
High: -0.90 V
Low: -1.70 V
b Disable tile pulse generator channell COMP (witil tile LED oft).
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