Sun Microsystems Ultra 1 Creator Series Service Manual page 199

8 bits of UPA 128, 4 bits of UPA 72, and 16 bits of DRAM bus per ASIC
3.3-VDC and 5-VDC power supply voltage
Switch connections controlled by SC
48-pin TSSOP package
C.2.4 Reset, Interrupt, Scan, and Clock Controller
The reset, interrupt, scan, and clock (RISC) ASIC implements four functions: reset,
interrupt, scan, and clock. Generation and stretching of the reset pulse is performed
in this ASIC. Interrupt logic concentrates 42 different interrupt sources into a 6-bit
code which communicates with the SYSIO ASIC. It also integrates a JTAG controller.
A highlight of the RISC ASIC features follow:
Determines system clock frequency
Controls reset generation
Provides JTAG
Performs SBus and miscellaneous interrupt concentration for SYSIO
Controls flash PROM programming, frequency margining, and lab console
operation
25-MHz operation
160-pin MQFP package
3.3-VDC and 5-VDC supply voltage
C.2.5 Frame Buffer Controller
The frame buffer controller (FBC) ASIC is the graphics draw ASIC that provides
interface between the UPA and the 3DRAM. The FBC ASIC provides 2D and 3D
graphics draw acceleration.
A highlight of the FBC ASIC features follow:
UPA slave device with write-mostly philosophy
Supports single buffered and double buffered with Z buffer configurations
Interfaces with 3DRAM to achieve accelerated graphics performance
Supports frame buffer to frame buffer copy
Supports viewport clipping, picking, and pixel processing
Supports byte, plane masks, raster operations, blend operations, and conditional
writes in 3DRAM
83/400-MHz UPA operation and 75-MHz 3DRAM operation
Appendix C Functional Description C-13