Sun Microsystems Ultra 1 Creator Series Service Manual page 190

Implements 44-bit virtual address bits and 41-bit physical address bits
Implements the visual instruction set (VIS) used by the FFB graphics device to
provide optimal graphics performance (this also includes instructions to help
with imaging performance)
16-Kbyte direct mapped data cache with 32-bit line size and 16-bit
sub-blocks. 16-Kbyte two-way set associate to a 32-bit line size
512-Kbyte external cache with 64-bit line size. Four synchronous SRAMs are used
for data and one SRAM is used for dual tags (DTAGs). Datapath to Ecache is 128
bits wide and parity protected.
System interface is provided through two instances of a Spitfire data buffer (SDB)
ASIC. System interface is 128 bits wide and is parity protected.
Features:
C.1.4 Memory
Memory uses conventional 5-VDC DRAM SIMMs (DSIMMs) with a
60-nanosecond access time. The system unit or server memory configuration allows
for 8 DSIMMs. Supported DSIMM sizes include 16-Mbyte, 32-Mbyte, 64-Mbyte, and
128-Mbyte.Memory capacities are as follows: 16-Mbyte DSIMMs, 128 Mbytes; 32-
Mbyte DSIMMs, 256 Mbytes; 64-Mbyte DSIMMs, 512 Mbytes; 128-Mbyte DSIMM, 1
Gbyte.
Memory configuration allows either one, two, three, or four DSIMM pairs to be
installed. DSIMM capacities must be identical in a DSIMM pair, however, DSIMM
pairs can be of different capacities, in which case the lower capacity DSIMM pair
will determine the capacity of the DSIMM pair.
C-4 Ultra 1 Creator Series Service Manual • August 1996
Specifies a 64-bit instruction set architecture
Provides for 64-bit data and addressing as well as other features to enhance
operating system and application performance
5-nanosecond or 6-nanosecond UltraSPARC processor.
Separate core and I/O power rails.
Air cooled using an impingement fan (SDB ASIC and SRAMs are cooled by
heatsink).
Two temperature levels: warning and shutdown.