Sun Microsystems Ultra 1 Creator Series Service Manual page 198

C.2.1 System Controller Uniprocessor
The system controller uniprocessor (SC-UP) ASIC is the key element for controlling
the UPA and main memory. The SC-UP ASIC controls accesses from UPA master
device to UPA slave device, and UPA accesses to memory. SC-UP includes a
complete coherency controller which controls system dual tags (DTAGs).
A highlight of the SC-UP ASIC features follow:
Integrates memory controller functionality
Supports four banks of memory, each with two SIMMs
Supports DSIMMs with 4-Mbyte, 16-Mbyte, 64-Mbyte, 60-nanosecond DRAM
Maximum memory configurations of 1 Gbytes with eight 128-Mbyte DSIMMs
Supports two UPA masters and one UPA slave with independent address busses
(independent busses are required for graphics streaming)
Controls the BMX ASIC which connects the UPA data bus and memory
83-MHz or 100-MHz operation
225-pin BGA package
3.3-VDC and 5-VDC power supply voltage
C.2.2 System I/O Controller
The system I/O controller (SYSIO) ASIC provides bridging between the UPA and
the SBUS.
A highlight of the SYSIO ASIC features follow:
Contains the IOMMU
Integrates streaming buffer to enhance sequential I/O performance
Provides logic for dispatching interrupt vectors to processors
Provides ECC generation and checking logic
Provides 372-pin BGA packaging
Provides 3.3-VDC and 5-VDC (for SBus) supply voltages
C.2.3 Buffered Memory Crossbar
The buffered memory crossbar (BMX) ASIC is a three-port crossbar connecting a
144-bit UPA data bus, a 288-bit-wide DRAM memory bus, and a 72-bit UPA data
bus. To maintain a manageable pin count, the devices are sliced so that 18 BMX
ASICs are needed to form the complete switch function.
A highlight of the BMX ASIC features follow:
C-12 Ultra 1 Creator Series Service Manual • August 1996