C
A P P E N D I X
Functional Description
This section provides a functional description for the Ultra 1 Creator Series system.
"Jumper Descriptions" on page 17
"Environmental Compliance" on page 21
"Agency Compliance" on page 21
C.1
System Unit/Server Overview
Refer to
UPA mechanism. The output of the UltraSPARC processor and the output of the
system I/O controller (SYSIO) ASIC reside on the UPA. A slave UPA port is
provided for graphic device communications between the fast frame buffer (FFB),
the buffered memory crossbar (BMX) ASIC, and the SYSIO ASIC. All UPA
interactions are orchestrated by the system controller uniprocessor
(SC-UP) ASIC.
The I/O sub-system connects to the processor-to-memory sub-system through the
SYSIO ASIC. The SYSIO ASIC provides connectivity to two SBus slots, the fast
Ethernet parallel port SCSI (FEPS) ASIC, the audio processor controller (APC) ASIC,
and the slave I/O (Slavio) ASIC.
. The processor-to-memory interconnection is provided by the
FIGURE C-1
C-1