Lenovo System x3650 M5 Installation And Service Manual page 199

Hide thumbs Also See for System x3650 M5:
Table of Contents

Advertisement

capacity over memory frequency, 3DPC (three DIMMs per channel) configuration is not recommended since
3DPC configuration forces the memory subsystem to run at a lower frequency (1600 MHz).
Refer to the
Understanding and Optimizing Memory Performance for Intel Xeon Processor E5-2600 v3 Series in
IBM Flex System, System x, and BladeCenter Platforms
Memory mirrored channel
Memory mirrored channel mode replicates and stores data on two pairs of DIMMs within two channels
simultaneously.
If a failure occurs, the memory controller switches from the primary pair of memory DIMMs to the backup
pair of DIMMs. To enable memory mirrored channel through the Setup Utility, select System Settings ➙
Memory. For more information, see "Using the Setup Utility" on page 51. When you use the memory
mirrored channel feature, consider the following information:
• When you use memory mirrored channel, you must install a pair of DIMMs at a time. The two DIMMs in
each pair must be identical in size, type, and rank (single, dual, or quad), and organization, but not in
speed. The channels run at the speed of the slowest DIMM in any of the channels.
• The maximum available memory is reduced to half of the installed memory when memory mirrored
channel is enabled. For example, if you install 64 GB of memory using RDIMMs, only 32 GB of
addressable memory is available when you use memory mirrored channel.
The following diagram lists the DIMM connectors on each memory channel.
Microprocessor 2
Figure 107. Connectors on each memory channel
The following table shows the installation sequence for memory mirrored channel mode:
Table 13. Memory mirrored channel mode DIMM population sequence
Number of installed microprocessors
1
2
CPU2
white paper for the detail.
Channel
DIMM connector population sequence
1, 4
9, 12
2, 5
8, 11
3, 6
7, 10
1, 4
13, 16
9, 12
21, 24
.
Chapter 5
Installing, removing, and replacing components
Microprocessor 1
CPU1
187

Advertisement

Table of Contents
loading

Table of Contents