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S3F80JB
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Stop Mode Release Timing When Initiated By An External Interrupt·························; Stop Mode Release Timing When Initiated By A Reset············································· - Samsung S3F80JB User Manual
8-bit cmos microcontrollers
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ELECTRICAL DATA (4MHz)
V
DD
Execution of
STOP Instrction
EXT INT
Figure 17-7. Stop Mode Release Timing When Initiated by an External Interrupt
V
DD
Execution of
STOP Instrction
nRESET
NOTE:
Figure 17-8. Stop Mode Release Timing When Initiated by a Reset
17-8
Stop Mode
Data Retention Mode
V
Stop Mode
t
is the same as 4096 x 16 x 1/f
WAIT
DDDR
0.2V
DD
Reset
Occur
0.85V
0.2V
DD
.
OSC
Idle Mode
(Basic Timer Active)
Normal Operating Mode
0.8V
DD
t
WAIT
Oscillation Stabilization Time
Normal
Operating
Mode
DD
t
WAIT
S3F80JB
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