Mapped Registers (Bank1, Set1) - Samsung S3F80JB User Manual

S3F80JB
Register Name
Counter A Control Register
Counter A Data Register (High Byte)
Counter A Data Register (Low Byte)
Timer 1 Counter Register (High Byte)
Timer 1 Counter Register (Low Byte)
Timer 1 Data Register (High Byte)
Timer 1 Data Register (Low Byte)
Timer 1 Control Register
STOP Control Register
Basic Timer Counter
External Memory Timing Register
Interrupt Priority Register
NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.
Register Name
LVD Control Register
Port 3 [4:5] Control Register
Port 4 Control Register (High Byte)
Port 4 Control Register (Low Byte)
Timer 2 Counter Register (High Byte)
Timer 2 Counter Register (Low Byte)
Timer 2 Data Register (High Byte)
Timer 2 Data Register (Low Byte)
Timer 2 Control Register
Comparator Mode Register
Comparison Result Register
Comparator Input Selection Register
Flash Memory Sector Address Register (High Byte)
Flash Memory Sector Address Register (Low Byte)
Flash Memory User Programming Enable Register
Flash Memory Control Register
NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.
Table 4-1. Mapped Registers (Continued)
Mnemonic
CACON
CADATAH
CADATAL
T1CNTH
T1CNTL
T1DATAH
T1DATAL
T1CON
STOPCON
Location FCH is not mapped.
BTCNT
EMT
IPR
Table 4-2. Mapped Registers (Bank1, Set1)
Mnemonic
P345CON
T2DATAH
T2DATAL
CMPREG
Not mapped in address F0H to 0FFH.
Decimal
243
244
245
246
247
248
249
250
251
253
254
255
Decimal
LVDCON 224
225
P4CONH 226
P4CONL 227
T2CNTH 228
T2CNTL 229
230
231
T2CON 232
CMOD 233
234
CMPSEL 235
FMSECH 236
FMSECL 237
FMUSR 238
FMCON 239
CONTROL REGISTERS
Hex R/W
F3H R/W
F4H R/W
F5H R/W
(NOTE)
F6H
R
(NOTE)
F7H
R
F8H R/W
F9H R/W
FAH R/W
FBH W
(NOTE)
FDH
R
FEH R/W
FFH R/W
Hex R/W
E0 R/W
E1 R/W
E2 R/W
E3 R/W
(NOTE)
E4
R
(NOTE)
E5
R
E6 R/W
E7 R/W
E8 R/W
E9 R/W
(NOTE)
EA
R
EB R/W
EC R/W
ED R/W
EE R/W
EF R/W
4-3