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RESET
STOP ERROR DETECTION & RECOVERY
When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to '0'and chip is in stop or abnormal state, the
falling edge input of P0 and P2.4-P2.7 generates the reset signal.
Refer to following table and figure for more information.
Table 8-1. Reset Condition in STOP Mode When IPOR / LVD Control Bit is "1" (always LVD-On)
Slope of V
DD
Rising up from
V
DD
V
< V
DD
LVD
V
DD
V
DD
Standstill
V
DD
≥ V
(V
)
DD
LVD
Table 8-2. Reset Condition in STOP Mode When IPOR / LVD Control Bit is "0"
Slope of V
DD
Rising up from
0.4 V
< V
<
DD
DD
V
LVD
Rising up from
V
< 0.4V
DD
DD
Standstill
≥ V
(V
)
DD
LVD
NOTE: IPOR / LVD control bit is included in smart option at address 003FH. (3FH.7)
8-8
Condition
V
The voltage level of reset pin
DD
≥ V
Vreset ≥ V
LVD
≥ V
Vreset < V
LVD
< V
Transition from
LVD
"Vreset < V
≥ V
Transition from
LVD
"Vreset < V
Condition
V
The voltage level of reset pin
DD
≥ V
Vreset ≥ V
V
DD
LVD
V
> V
Vreset < V
DD
LVD
V
< V
Transition from
DD
LVD
"Vreset < V
≥ V
Vreset ≥ V
V
DD
LVD
V
> V
Vreset < V
DD
LVD
V
< V
Transition from
DD
LVD
"Vreset < V
≥ V
Transition from
V
DD
LVD
"Vreset < V
(Vreset)
IH
IH
" to "V
< Vreset"
IL
IH
" to "V
< Vreset"
IL
IH
(Vreset)
IH
IH
" to "V
< Vreset"
IL
IH
IH
IH
" to "V
< Vreset"
IL
IH
" to "V
< Vreset"
IL
IH
Reset
System Reset
Source
LVD circuit
System reset occurs
–
No system reset
–
No system reset
Reset pin
System reset occurs
Reset
System Reset
Source
–
No system reset
–
No system reset
–
No system reset
Internal POR
System reset occurs
–
No system reset
–
No system reset
Reset pin
System reset occurs
S3F80JB
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