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Unbuffered DIMM
17. Timing Parameters by Speed Grade
[ Table 21 ] Timing Parameters by Speed Bin
Speed
Parameter
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Clock Period
Average high pulse width
Average low pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Cumulative error across n = 13, 14 ... 49, 50 cycles
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
Data setup time to DQS, DQS referenced to
V
(AC)V
(AC) levels
IH
IL
Data hold time from DQS, DQS referenced to
V
(AC)V
(AC) levels
IH
IL
Data setup time to DQS, DQS referenced to
V
(AC)V
(AC) levels
IH
IL
DQ and DM Input pulse width for each input
datasheet
DDR3-800
Symbol
MIN
MAX
tCK(DLL_OF
8
-
F)
tCK(avg)
tCK(avg)min +
tCK(avg)max +
tCK(avg)min +
tCK(abs)
tJIT(per)min
tJIT(per)max
tCH(avg)
0.47
0.53
tCL(avg)
0.47
0.53
tJIT(per)
-100
100
tJIT(per, lck)
-90
90
tJIT(cc)
200
tJIT(cc, lck)
180
tERR(2per)
- 147
147
tERR(3per)
- 175
175
tERR(4per)
- 194
194
tERR(5per)
- 209
209
tERR(6per)
- 222
222
tERR(7per)
- 232
232
tERR(8per)
- 241
241
tERR(9per)
- 249
249
tERR(10per)
- 257
257
tERR(11per)
- 263
263
tERR(12per)
- 269
269
tERR(nper)
tCH(abs)
0.43
-
tCL(abs)
0.43
-
tDQSQ
-
200
tQH
0.38
-
tLZ(DQ)
-800
400
tHZ(DQ)
-
400
tDS(base)
-
90
AC160
tDS(base)
-
75
AC175
tDH(base)
-
160
DC90
tDH(base)
-
150
DC100
tDS(base)
-
140
AC135
tDS(base)
-
125
AC150
-
tDIPW
600
DDR3-1066
DDR3-1333
MIN
MAX
MIN
8
-
8
See Speed Bins Table
tCK(avg)max +
tCK(avg)min +
tCK(avg)max +
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
0.47
0.53
0.47
0.47
0.53
0.47
-90
90
-80
-80
80
-70
180
160
160
140
- 132
132
- 118
- 157
157
- 140
- 175
175
- 155
- 188
188
- 168
- 200
200
- 177
- 209
209
- 186
- 217
217
- 193
- 224
224
- 200
- 231
231
- 205
- 237
237
- 210
- 242
242
- 215
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
0.43
-
0.43
0.43
-
0.43
-
150
-
0.38
-
0.38
-600
300
-500
-
300
-
1.35V
-
40
-
1.5V
-
25
-
1.35V
-
110
75
1.5V
-
100
65
1.35V
-
90
45
1.5V
-
75
30
-
490
400
- 30 -
DDR3L SDRAM
DDR3-1600
Units
MAX
MIN
MAX
-
8
-
ns
ps
tCK(avg)min +
tCK(avg)max +
ps
tJIT(per)min
tJIT(per)max
0.53
0.47
0.53
tCK(avg)
0.53
0.47
0.53
tCK(avg)
80
-70
70
ps
70
-60
60
ps
140
ps
120
ps
118
-103
103
ps
140
-122
122
ps
155
-136
136
ps
168
-147
147
ps
177
-155
155
ps
186
-163
163
ps
193
-169
169
ps
200
-175
175
ps
205
-180
180
ps
210
-184
184
ps
215
-188
188
ps
ps
-
0.43
-
tCK(avg)
-
0.43
-
tCK(avg)
125
-
100
ps
-
0.38
-
tCK(avg)
250
-450
225
ps
250
-
225
ps
-
-
-
ps
-
-
-
ps
-
55
-
ps
-
45
-
ps
-
25
-
ps
-
10
-
ps
-
-
360
ps
Rev. 1.0
NOTE
6
24
25
26
13
13, g
13,14, f
13,14, f
d, 17
d, 17
d, 17
d, 17
28
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