Reset Sources Of The S3F80Jb - Samsung S3F80JB User Manual

RESET
IPOR / LVD Contorl Bit '1'
(smart option bit[7] @03FH)
IPOR / LVD Contorl Bit '1'
(smart option bit[7] @03FH)
STOP
IPOR
Watchdog Timer
nRESET
P0&P2
(INT0-INT9)
(EI)external interrupt enable
(smart option bit[7] @03FH)
IPOR / LVD Contorl Bit '1'
P0 & P2.4-2.7
(smart option bit[7] @03FH)
IPOR / LVD Contorl Bit '1'
1. When IPOR/LVD Control Bit of smart option is set to '1', the rising edge detection of LVD circuit while rising of
VDD passes the level of VLVD.
2. When IPOR/LVD Control Bit of smart option is set to '0' and mode is in STOP Mode, reset is generated by
internal power-on reset.
3. Basic Timer over-flow for watchdog timer. See the chapter 11. Basic Timer and Timer 0 for more
understanding.
4. The reset pulse generation by transiting of reset pin (nRESET) from low level to high level on the condition
that VDD is higher level state than VLVD (Low level Detect Voltage).
5. When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to '0' and chip is in stop mode, external
interrupt input by P0 and P2 regardless of external interrupt enable/disable generates the reset signal.
8-2
STOP
LVD
STOP
STOP
Figure 8-1. RESET Sources of The S3F80JB
S3F80JB
1
2
3
RESET
4
5
6