Counter A Block Diagram - Samsung S3F80JB User Manual

COUNTER A
DIV 1
DIV 2
DIV 4
DIV 8
CACON.2
f
OSC
NOTE:
12-2
CACON.6-.7
CLK
MUX 16-Bit Down Counter
Repeat
Control
Interrupt
Control
Low Byte Register
CACON.4-.5
High Byte Register
The value of the CADATAL register is loaded into the 8-bit counter when the
operation of the counter A stars. If a borrow occurs, the value of the
CADATAH register is loaded into the 8-bit counter. However, if the next borrow
occurs, the value of the CADATAL register is loaded into the 8-bit counter.
Figure 12-1. Counter A Block Diagram
MUX
INT. GEN.
Counter A Data
Counter A Data
Data Bus
CACON.0
To Other Block
(CAOF)
(P3.1/REM)
CACON.3
IRQ2
(CAINT)
S3F80JB