Timer 0 Data Register (T0Data); Timer 0 Control Register (T0Con) - Samsung S3F80JB User Manual

S3F80JB
MSB
Timer 0 Input Clock Selection Bits:
00 = f /4096
OSC
01 = f /256
OSC
10 = f /8
OSC
11 = External clock
01 = Capture mode (capture on rising edge, counter running, OVF can occur)
10 = Capture mode (capture on falling edge, counter running, OVF can occur)
NOTE: The external clock source of timer 0 is P3.1/T0CK in 32-pin package, or P3.2/T0CK in 44-pin package.
MSB

Timer 0 Control Register (T0CON)

D2H, Set 1, Bank0 , R/W
.7 .6 .5 .4
(NOTE)
Timer 0 Operating Mode Selection Bits:
00 = Interval mode
11 = PWM mode (OVF interrupt can occur)
Figure 10-2. Timer 0 Control Register (T0CON)

Timer 0 Data Register (T0DATA)

D1H, Set1, Bank 0 , R/W
.7 .6 .5
Figure 10-3. Timer 0 DATA Register (T0DATA)
.3 .2 .1 .0
Timer 0 Interrupt Match/capture Enable Bit:
Timer 0 Overflow Interrupt Enable Bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 0 Counter Clear Bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
.4 .3 .2 .1
Reset Value: FFH
BASIC TIMER and TIMER 0
LSB
Timer 0 Interrupt Pending Bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending
0 = Disable interrupt
1 = Enable interrupt
.0 LSB
10-5