Stop Mode Release Timing When Initiated By A Lvd ··············································· - Samsung S3F80JB User Manual

8-bit cmos microcontrollers
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S3F80JB
V
DD
V
LVD
Execution of
STOP Instrction
NOTE:
t
WAIT
Figure 17-9. Stop Mode Release Timing When Initiated by a LVD
= – 25 °C to + 85 °C)
(T
A
Parameter
Input
Capacitance
Output
Capacitance
I/O Capacitance
= – 25 °C to + 85 °C)
(T
A
Parameter
Interrupt Input
High, Low Width
nRESET Input
Low Width
Stop Mode
is the same as 4096 x 16 x 1/f
Table 17-5. Input/Output Capacitance
Symbol
Conditions
C
f = 1 MHz
IN
V
= 0 V, unmeasured pins
DD
C
are connected to V
OUT
C
IO
Table 17-6. A.C. Electrical Characteristics
Symbol
Conditions
t
P0.0–P0.7, P2.0–P2.7
,
INTH
V
t
3.6 V
=
DD
INTL
t
Input
RSL
V
3.6 V
=
DD
Reset
Oscillation Stabilization Time
Occur
Back-up Mode
V
DDDR
Data Retention Time
.
OSC
Min
SS
Min
200
1000
ELECTRICAL DATA (4MHz)
Normal Operating Mode
t
WAIT
Typ
Max
10
Typ
Max
300
Unit
pF
Unit
ns
17-9

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