TIMER 2
Figure 13-5. Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL)
13-6
Timer2 Counter High-Byte Register (T2CNTH)
E4H , Set 1, Bank 1, Read-only
MSB
.7
.6
.5
Timer 2 Counter Low-Byte Register (T2CNTL)
E5H , Set 1, Bank 1, Read-only
MSB
.7
.6
.5
Timer 2 Data High-Byte Register (T2DATAH)
E6H , Set 1, Bank 1, R/W
MSB
.7
.6
.5
Timer 2 Data Low-Byte Register (T2DATAL)
E7H , Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
Reset Value: 00H
.4
.3
.2
.1
Reset Value: 00H
.4
.3
.2
.1
Reset Value: FFH
.4
.3
.2
.1
Reset Value: FFH
.0
LSB
.0
LSB
.0
LSB
.0
LSB
S3F80JB