P0Pnd Port 0 External Interrupt Pending Register - Samsung S3F80JB User Manual

8-bit cmos microcontrollers
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CONTROL REGISTERS
P0PND
— Port 0 External Interrupt Pending Register
Bit Identifier
Reset Value
Read/Write
Addressing Mode
.7
.6
.5
.4
.3
.2
.1
.0
NOTE: To clear an interrupt pending condition, write a "0" to the appropriate pending flag bit. Writing a "1" to an interrupt
pending flag (P0PND.7–0) has no effect.
4-22
.7
.6
0
0
R/W
R/W
Register addressing mode only
P0.7 External Interrupt (INT4) Pending Flag Bit (see Note)
0
No P0.7 external interrupt pending (when read)
1
P0.7 external interrupt is pending (when read)
P0.6 External Interrupt (INT4) Pending Flag Bit
0
No P0.6 external interrupt pending (when read)
1
P0.6 external interrupt is pending (when read)
P0.5 External Interrupt (INT4) Pending Flag Bit
0
No P0.5 external interrupt pending (when read)
1
P0.5 external interrupt is pending (when read)
P0.4 External Interrupt (INT4) Pending Flag Bit
0
No P0.4 external interrupt pending (when read)
1
P0.4 external interrupt is pending (when read)
P0.3 External Interrupt (INT3) Pending Flag Bit
0
No P0.3 external interrupt pending (when read)
1
P0.3 external interrupt is pending (when read)
P0.2 External Interrupt (INT2) Pending Flag Bit
0
No P0.2 external interrupt pending (when read)
1
P0.2 external interrupt is pending (when read)
P0.1 External Interrupt (INT1) Pending Flag Bit
0
No P0.1 external interrupt pending (when read)
1
P0.1 external interrupt is pending (when read)
P0.0 External Interrupt (INT0) Pending Flag Bit
0
No P0.0 external interrupt pending (when read)
1
P0.0 external interrupt is pending (when read)
.5
.4
.3
0
0
R/W
R/W
R/W
F2H
Set1 Bank0
.2
.1
0
0
0
R/W
R/W
S3F80JB
.0
0
R/W

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