Table of Contents
Advertisement
RESET
BACK-UP MODE
For reducing current consumption, S3F80JB goes into Back-up mode. If external reset pin is low state or a falling
level of V
is detected by LVD circuit on the point of V
DD
peripheral operation were stopped due to oscillation stop, the supply current is reduced. In back-up mode, chip
cannot be released from stop state by any interrupt. The only way to release back-up mode is the system-reset
operation by interactive work of reset pin and LVD circuit. The system reset of watchdog timer is not occurred in
back up mode.
LVD
nRESET
Voltage [V]
V
DD
V
LVD
Low level
detect voltage
Falling edge detected,
Normal Operation
NOTES:
1, When the rising edge is detected by LVD circuit, Back-up mode is relesased. (V
2. When the falling edge is detected by LVD circuit, Back-up mode is activated (V
Figure 8-8. Timing Diagram for Back-up Mode Input and Released by LVD
8-10
Rising Edge
Detector
Falling Edge
Detector
Noise
Filter
Figure 8-7. Block Diagram for Back-up Mode
Rising edge detected
(V
oscillation stop.
(V
< V
)
DD
LVD
, chip goes into the back-up mode. Because CPU and
LVD
V
< = V
D D
LV D
V
< = V
reset
I L
Slope of nRESET & V
>= V
)
DD
LVD
Back up Mode
Back-Up Mode
Pin
DD
Reset Pulse generated,
oscillation starts
Normal Operation
LVD
> V
LVD
S3F80JB
=
V
)
DD
)
DD
Advertisement
Table of Contents
