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S3F80JB
TIMER 1 MATCH INTERRUPT
Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value
matches the value that is written to the Timer 1 reference data registers, T1DATAH and T1DATAL. When a match
condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and
up counting resumes from '00H'.
In match mode, program software can poll the Timer 1 match/capture interrupt pending bit, T1CON.0, to detect
when a Timer 1 match interrupt pending condition exists (T1CON.0 = "1"). When the interrupt request is
acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear
the interrupt pending condition by writing a "0" to T1CON.0.
CLK
Figure 11-2. Simplified Timer 1 Function Diagram: Interval Timer Mode
Interrupt
Enable/Disable
(T1CON.1)
R (Clear)
16-Bit Up Counter
Match
16-Bit Comparator
Timer 1 High/Low
Buffer Register
Timer 1 Data High/Low
Buffer Register
IRQ1 (T1INT)
Pending
(T1CON.0)
CTL
T1CON.5
T1CON.4
Match Signal
T1CON.3
TIMER 1
P3.0 or P3.3
11-3
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