Ipr Interrupt Priority Register - Samsung S3F80JB User Manual

CONTROL REGISTERS
IPR
— Interrupt Priority Register
Bit Identifier
Reset Value
Read/Write
Addressing Mode
.7, .4, and .1
.6
.5
.3
.2
.0
NOTE: The S3F80JB interrupt structure uses eight levels: IRQ0-IRQ7.
4-16
.7 .6
x x
R/W R/W
Register addressing mode only
Priority Control Bits for Interrupt Groups A, B, and C
0 0 0 Group priority undefined
0 0 1 B > C > A
0 1 0 A > B > C
0 1 1 B > A > C
1 0 0 C > A > B
1 0 1 C > B > A
1 1 0 A > C > B
1 1 1 Group priority undefined
Interrupt Subgroup C Priority Control Bit
0 IRQ6 > IRQ7
1 IRQ7 > IRQ6
Interrupt Group C Priority Control Bit
0 IRQ5 > (IRQ6, IRQ7)
1 (IRQ6, IRQ7) > IRQ5
Interrupt Subgroup B Priority Control Bit
0 IRQ3>IRQ4
1 IRQ4>IRQ3
Interrupt Group B Priority Control Bit
0 IRQ2 >(IRQ3, IRQ4)
1 (IRQ3, IRQ4) > IRQ2
Interrupt Group A Priority Control Bit
0 IRQ0 > IRQ1
1 IRQ1 > IRQ0
.5 .4 .3
x x
R/W R/W R/W
(See Note)
(See Note)
FFH Set1 Bank0
.2 .1
x x x
R/W R/W
S3F80JB
.0
x
R/W