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Figure
Number
12-1
12-2
12-3
12-4
13-1
13-2
13-3
13-4
13-5
14-1
14-2
14-3
14-4
14-5
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
16-1
16-2
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
xii
List of Figures
Counter A Block Diagram .........................................................................................12-2
Counter A Control Register (CACON) ......................................................................12-3
Counter A Registers .................................................................................................12-3
Counter A Output Flip-Flop Waveforms in Repeat Mode..........................................12-5
Simplified Timer 2 Function Diagram: Capture Mode ...............................................13-2
Simplified Timer 2 Function Diagram: Interval Timer Mode ......................................13-3
Timer 2 Block Diagram .............................................................................................13-4
Timer 2 Control Register (T2CON) ...........................................................................13-5
Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL).................................13-6
Comparator Block Diagram for The S3F80JB...........................................................14-2
Conversion Characteristics.......................................................................................14-3
Comparator Mode Register (CMOD) ........................................................................14-4
Comparator Input Selection Register (CMPSEL) ......................................................14-4
Comparator Result Register (CMPREG) ..................................................................14-5
Program Memory Address Space.............................................................................15-3
Smart Option ............................................................................................................15-4
Flash Memory Control Register (FMCON)................................................................15-6
Flash Memory User Programming Enable Register (FMUSR)..................................15-6
Flash Memory Sector Address Register (FMSECH) .................................................15-7
Flash Memory Sector Address Register (FMSECL)..................................................15-7
Sector Configurations in User Program Mode ..........................................................15-8
Sector Erase Flowchart in User Program Mode........................................................15-9
Byte Program Flowchart in a User Program Mode....................................................15-13
Program Flowchart in a User Program Mode............................................................15-14
Low Voltage Detect (LVD) Block Diagram ································································16-2
Low Voltage Detect Control Register (LVDCON)······················································16-3
Typical Low-Side Driver (Sink) Characteristics (P3.1 only) ·······································17-5
Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3) ·························17-5
Typical Low-Side Driver (Sink) Characteristics
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ··························································17-6
Typical High-Side Driver (Source) Characteristics (P3.1 only)··································17-6
Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3) ····················17-7
Typical High-Side Driver (Source) Characteristics
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ··························································17-7
Stop Mode Release Timing When Initiated by an External Interrupt ·························17-8
Stop Mode Release Timing When Initiated by a Reset·············································17-8
Stop Mode Release Timing When Initiated by a LVD ···············································17-9
Input Timing for External Interrupts (Port 0 and Port 2) ············································17-10
Input Timing for Reset (nRESET Pin) ·······································································17-10
Operating Voltage Range of S3F80J9 ······································································17-13
(Continued)
Title
Number
S3F80JB MICROCONTROLLER
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