Basic Timer And Timer 0 Block Diagram - Samsung S3F80JB User Manual

S3F80JB
X DIV
IN
R
Bit 0
R
X DIV
IN
P3.1/T0CK
or
P3.2/T0CK
(note 3)
P3.0/T0CAP
Bits 5, 4
NOTES:
1. During a power-on reset operation, the CPU is idle during the required oscillation
stabilization interval (until bit 4 of the basic timer counter overflows).
2. It is available only in using internal mode.
3. The external clock source is P3.1/T0CK in 32-pin package, or P3.2/T0CK in 42/44-pin package.
Bit 1
Bits 3, 2
1/4096
8-Bit Up Counter
1/1024 MUX
(BTCNT, Read-Only)
1/128
Bits 7, 6
1/4096
1/256
8-Bit Up-Counter
1/8
MUX
GND 8-Bit Compatator
Timer 0 Data Register
Figure 10-7. Basic Timer and Timer 0 Block Diagram
RESET or STOP
Data Bus
Clear
When BTCNT.4 is set after releasing from
RESET or STOP mode, CPU clock starts.
Data Bus
R
(T0CNT)
Match
Timer 0 Buffer
Register
Bits 5, 4
(T0DATA)
Data Bus
BASIC TIMER and TIMER 0
Basic Timer Control Register
(Write '1010xxxxB' to disable.)
OVF
Bit 2
OVF IRQ0
(Timer 0 Overflow)
Bit 3
Clear
Bit 1
(2)
Bit 0
T0PWM
Match Signal
T0CON.3
T0OVF
Basic Timer Control Register
Timer 0 Control Register
RESET
IRQ0
(Timer 0 Match)
10-9