Booting Option - Samsung S5PV210 Hardware Design Manual

S5PV210_HARDWARE DESING GUIDE REV 1.0

4.2. Booting Option

OM[5:0] pin should be tied with VDDSYS or GND, directly. It is aimed for minimize leakage current when entering the
sleep mode. But if you have to get an option, you should add a pull-up and pull-down resistor with 100K ohms over.
OM[5] OM[4] OM[3]
1'b0
1'b0
1'b0 1'b1
1'b1 1'b0
1'b0
1'b1 1'b0
1'b1
Note) If OM[5] is set to 1, It is used for debug mode that UART boot is first and USB boot is second. UART boot has
some kind of error case. In case of UART error, the iROM boot sequence moves to second USB boot. USB boot also
has some kind of error case like UART. If USB boot is fail, boot sequence move to main memory boot.
Please refer to iROM application note which is more detail about error case.
OM[2] OM[1] OM[0]
1'b0
1'b0
1'b1
1'b0
1'b0
1'b1
1'b1
1'b0
1'b0
1'b1
1'b1
1'b0
1'b1
1'b1
1'b0
1'b0
1'b1
1'b0
1'b0
1'b1
1'b1
1'b0
1'b0
1'b1
1'b1
1'b0
1'b1
1'b1
1'b0
1'b1
1'b1
1'b0
1'b0
1'b1
1'b1
1'b0
1'b0
1'b1
1'b1
1'b0
1'b1
1'b1
1'b0
1'b0
1'b1
1'b0
1'b0
1'b1
1'b1
1'b0
1'b0
1'b1
1'b1
1'b0
1'b1
1'b1
1'b0
1'b0
1'b1
1'b0
1'b0
1'b1
1'b1
1'b0
1'b0
1'b1
1'b1
1'b0
1'b1
1'b1
OM[5] OM[4] OM[3]
I-ROM
Boot
Mode
I-ROM
(Nand 4KB, 5cycle)
First
boot
OnenandMux(Audi)
UART
->USB
OnenandDemux(Audi)
OM[2] OM[1]
eSSD
Nand 2KB, 5cycle
(Nand 8bit ECC)
Nand 4KB, 5cycle
(Nand 8bit ECC)
Nand 4KB, 5cycle
(Nand 16bit ECC)
OnenandMux
OnenandDemux
SD/MMC
eMMC(4-bit)
Reserved
Nand 2KB, 4cycle
(Nand 8bit ECC)
iROM NOR boot
eMMC(8-bit)
eSSD
Nand 2KB, 5cycle
Nand 4KB, 5cycle
Nand 16bit ECC
SD/MMC
eMMC(4-bit)
OM[0]
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
X-TAL
X-TAL(USB)
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