Smb36-Smb45 (Hsc0), Smb46-Smb55 (Hsc1), Smb56-Sm65 (Hsc2), Smb136-Smb145 (Hsc3), Smb146-Smb155 (Hsc4), Smb156-Smb165 (Hsc5): High-Speed Counters - Siemens SIMATIC S7 System Manual

Special memory (SM) and system symbol names
D.14 SMB36-SMB45 (HSC0), SMB46-SMB55 (HSC1), SMB56-SM65 (HSC2), SMB136-SMB145 (HSC3),
SMB146-SMB155 (HSC4), SMB156-SMB165 (HSC5): high-speed counters
D.14 SMB36-SMB45 (HSC0), SMB46-SMB55 (HSC1), SMB56-SM65
(HSC2), SMB136-SMB145 (HSC3), SMB146-SMB155 (HSC4),
SMB156-SMB165 (HSC5): high-speed counters
These bytes provide configuration and operation information for the high-speed counters:
● HSC0
● HSC1
● HSC2
● HSC3
● HSC4
● HSC5
Table D- 9 HSC0 configuration and operation
S7-200 SMART
symbol name
HSC0_Status
HSC0_Status_5
HSC0_Status_6
HSC0_Status_7
HSC0_Ctrl
HSC0_Reset_Level
HSC0_Rate
HSC0_Dir
HSC0_Dir_Update
HSC0_PV_Update
HSC0_CV_Update
HSC0_Enable
810
SM address Description
SMB36 HSC0 counter status
Note: Counter status bits are valid only while the CPU is executing an inter-
rupt routine that a high-speed counter event triggered.
SM36.0–SM36.4 Reserved
SM36.5 HSC0 current counting direction status bit: TRUE: Counting up
SM36.6 HSC0 current value equals preset value status bit: TRUE: Equal
SM36.7 HSC0 current value is greater than preset value status bit: TRUE: Greater
than
SMB37 HSC0 counter control
SM37.0 HSC0 active level control bit for Reset: FALSE: Reset is active high, TRUE:
Reset is active low
SM37.1 Reserved
SM37.2 HSC0 counting rate selection for Quadrature counters: FALSE: 4x counting
rate; TRUE: 1x counting rate
SM37.3 HSC0 direction control bit: TRUE: Count up
SM37.4 HSC0 update direction: TRUE: update direction
SM37.5 HSC0 update preset value: TRUE: Write new preset value to HSC0 preset
SM37.6 HSC0 update current value: TRUE: Write new current value to HSC0 cur-
rent
SM37.7 HSC0 enable bit: TRUE: enable
System Manual, V2.3, 07/2017, A5E03822230-AF
S7-200 SMART