Siemens SIMATIC S7 System Manual page 715

Table A- 54 CPU features
Technical data
User Program
memory
User data (V)
Retentive
On-board digital I/O
Process image
Analog image
Bit memory (M)
Temporary (local) memory
(L)
Sequential control relays
(S)
Expansion modules ex-
pansion
Signal board expansion
High- Total
speed
Single phase
counters
A/B phase
Pulse outputs
2
Pulse catch inputs
Cyclic interrupts
Edge interrupts
Memory card
Real time clock accuracy
Real time clock retention
time
You can configure areas of V memory, M memory, C memory (current values) and portions of T memory (current values
1
on retentive timers) to be retentive, up to the specified maximum amount.
The specified maximum pulse frequency is possible only for CPU models with transistor outputs. Pulse output operation
2
is not recommended for CPU models with relay outputs.
S7-200 SMART
System Manual, V2.3, 07/2017, A5E03822230-AF
CPU ST60 DC/DC/DC
30 Kbytes
20 Kbytes
10 Kbytes max.
1
36 inputs/24 outputs
256 bits of inputs (I) / 256 bits
of outputs (Q)
56 words of inputs (AI) / 56
words of outputs (AQ)
256 bits
64 bytes in the main program
and 64 bytes in each subrou-
tine and interrupt routine
60 bytes when programming
in LAD or FBD (STEP 7-
Micro/WIN reserves 4 bytes)
256 bits
6 max.
1 max.
6
4 at 200 kHz
2 at 30 kHz
2 at 100 kHz
2 at 20 kHz
3 at 100 kHz
14
2 at 1 ms resolution
4 rising and 4 falling (6 and 6
with optional signal board)
microSDHC card (optional)
120 seconds/month
7 days typ./6 days min. at 25
°C
CPU SR60 AC/DC/Relay
30 Kbytes
20 Kbytes
10 Kbytes max.
1
36 inputs/24 outputs
256 bits of inputs (I) / 256 bits
of outputs (Q)
56 words of inputs (AI) / 56
words of outputs (AQ)
256 bits
64 bytes in the main program
and 64 bytes in each subrou-
tine and interrupt routine
60 bytes when programming
in LAD or FBD (STEP 7-
Micro/WIN reserves 4 bytes)
256 bits
6 max.
1 max.
6
4 at 200 kHz
2 at 30 kHz
2 at 100 kHz
2 at 20 kHz
3 at 100 kHz
14
2 at 1 ms resolution
4 rising and 4 falling (6 and 6
with optional signal board)
microSDHC card (optional)
120 seconds/month
7 days typ./6 days min. at 25
°C
Technical specifications
A.2 S7-200 SMART CPUs
CPU CR60s AC/DC/Relay
12 Kbytes
8 Kbytes
2 Kbytes max.
1
36 inputs/24 outputs
256 bits of inputs (I) / 256 bits
of outputs (Q)
Not available
256 bits
64 bytes in the main program
and 64 bytes in each subrou-
tine and interrupt routine
60 bytes when programming
in LAD or FBD (STEP 7-
Micro/WIN reserves 4 bytes)
256 bits
Not available
Not available
4
4 at 100 kHz
2 at 50 kHz
Not available
Not available
2 at 1 ms resolution
4 rising and 4 falling
Not available
Not available
Not available
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