Priority group
Timed
Lowest Priority
E.3
High-speed counter summary
Clock A
Direction
/ Clock B
HSC0
I0.0
I0.1
HSC1
I0.1
HSC2
I0.2
I0.3
HSC3
I0.3
HSC4
I0.6
I0.7
S7-200 SMART
System Manual, V2.3, 07/2017, A5E03822230-AF
Event
Description
10
Timed interrupt 0 SMB34
11
Timed interrupt 1 SMB35
21
Timer T32 CT=PT interrupt
22
Timer T96 CT=PT interrupt
Reset
Single phase / Dual phase maximum
clock / input rate
I0.4
S model CPUs:
200 kHz
•
C model CPUs:
100 kHz
•
S model CPUs:
200 kHz
•
C model CPUs:
100 kHz
•
I0.5
S model CPUs:
200 kHz
•
C model CPUs:
100 kHz
•
S model CPUs:
200 kHz
•
C model CPUs:
100 kHz
•
I1.2
SR30 and ST30 model CPUs:
200 kHz
•
SR20, ST20, SR40, ST40, SR60,
and ST60 model CPUs:
30 kHz
•
AB quadrature phase maximum
clock / input rate
S model CPUs:
1
•
•
C model CPUs:
2
•
•
S model CPUs:
•
•
C model CPUs:
•
•
SR30 and ST30 model CPUs:
•
•
SR20, ST20, SR40, ST40, SR60, and
ST60 model CPUs:
•
•
References
E.3 High-speed counter summary
100 kHz = Maximum 1x count rate
400 kHz = Maximum 4x count rate
50 kHz = Maximum 1x count rate
200 kHz = Maximum 4x count rate
100 kHz = Maximum 1x count rate
400 kHz = Maximum 4x count rate
50 kHz = Maximum 1x count rate
200 kHz = Maximum 4x count rate
100 kHz = Maximum 1x count rate
400 kHz = Maximum 4x count rate
20 kHz = Maximum 1x count rate
80 kHz = Maximum 4x count rate
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