Siemens SIMATIC S7 System Manual page 271

Reset operation
The operation of reset shown in the following figure applies to all modes that use the reset
input. In the figure below, the reset operation is shown with the active state assigned as the
high level.
HSC reset
HDEF instruction sets the reset active level and counting rate
HSC0, HSC2, HSC4, and HSC5 counters have two control bits that are used to configure the
active state of the reset and to select 1x or 4x counting modes (AB quadrature phase
counters only). These bits are located in the HSC control byte for the respective counter and
are only used when the HDEF instruction is executed. These bits are defined in the following
table.
Note
You must set these two control bits to the desired state before the HDEF instruction is
executed. Otherwise, the counter takes on the default configuration for the counter mode
selected.
Once the HDEF instruction has been executed, you cannot change the counter setup unless
you first place the CPU in STOP mode.
S7-200 SMART
System Manual, V2.3, 07/2017, A5E03822230-AF
Program instructions
7.6 Counters
271