Key Features Of S3F84B8 - Samsung S3F84B8 Design Manual

S3F84B8_ALL-IN-ONE IH COOKER_AN_REV 0.00

1.2 KEY FEATURES OF S3F84B8

With no more discrete ICs like LM339 (comparator IC) in previous IHC solutions, S3F84B8 successfully integrates
four comparators, one OPA, and one IH-PWM to control power directly. After configuration, all the four
comparators can cooperate with the IH-PWM automatically, which makes the time-sensitive control possible.
Figure2 shows the pin assignment in S3F84B8.
The key features of S3F84B8 include:

8K Full Flash ROM and 272B SRAM

Four Comparators

One OPA

10-bit IH-PWM x 1 (can co-operate with the four Comparators)

10-bit ADC x 8

8-bit Basic Timer (can be used as Watch Dog Timer)

8-bit TimerA

16-bit Timer0 (can be used as two 8-bit Timers C/D)

External Interrupts X 6

Supports configurable LVR (1.9/2.3/3.6/3.9V)

Supports configurable internal RC (0.5M/8MHz RC @5V with maximum 3% accuracy)

Supports 18 IOs (maximum) when using internal LVR and internal RC
Comparator0 has two inputs. Its output can trigger the PWM to start a new cycle immediately or after some
programmable delay. This helps in the synchronization control. The delay can adjust the IGBT to turn on at
minimum collector voltage, thereby reducing the heat and protecting the transistor.
V 1
SS
INT0/X /P0.0 2
IN
INT1/X /P0.1 3
OUT
V /nRESET/P0.2 4
PP
BUZ/INT2/P0.3 5
PWM/INT3/P0.4 6
INT4/P0.5 7
TAOUT/INT5/P0.6 8
TACK/CMP0_P/P1.0 9
TACAP/CMP0_N/P1.1 10
Figure 1-2
20 V
19 P2.7/ADC7/(SCL)
18 P2.6/ADC6/(SDA)
17 P2.5/ADC5/CMP3_N
S3F84B8 16 P2.4/ADC4/CMP2_N
15 P2.3/ADC3(OPA_O)
20-DIP/
20-SOP
14 P2.2/ADC2/OPA_N
13 P2.1/ADC1/OPA_P
12 P2.0/ADC0/TDOUT
11 P1.2/CMP1_N
Pin Assignment in S3F84B8
1-2
1 OVERVIEW OF IH COOKER (IHC)
DD