Intel IXP28XX Manual page 153

address/data
routing guidelines 133
signals 132
topology 133
clock
signals 132
topology 132
control signals 130
data multiplexing and demultiplexing 137
read transactions 142
write transactions 138
flash memory and microprocessor interface support 133
flash PROM interface
address latch logic 134
logic 134
interface 128
microprocessor interface
address latch logic 136
logic 136
signals 130
summary 145
topology and routing 130
SPCI
address/data signals 116
with IDSEL 118
bus interface 116
clock signals 117
SPI-4.2, Media and Switch Fabric (MSF) 101
SRAM
controller configurations 54
interface
base card side 81
coprocessor interface 81
QDR
address topology 65
clock topologies
connections 57
control topologies, RPE#, WPE#, BWE# 76
DataIn topology 70
DataOut topology 68
design review checklist 94
interface 57
output timing specifications 64
placement with TCAM 90
routing 84
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guidelines 132
C, C#, CIN, CIN# 74
K, K# 71
alternating layers 89
rules 65
with TCAM 93
recommendations 92
using x9 versus x18 parts 58
VREF generation 79
QDRII Loopback length 85
Supply voltage, power-up sequence 24
System overview 11
T
TCAM
interface 81
base card side 81
placement with QDR SRAM 90
routing
with QDR SRAM 93
recommendations 92
TCAM/SRAM/coprocessor interface 81
base card side 81
Timing
processor input 64
processor output 64
Topology
routing four-QDR SRAM 84
Slowport 130
address and data signals 133
clock 132
guidelines 132
Trace
LVDS
characteristics for ISDP2800 platform 104
requirements 104
package lengths
LVDS_Diff signals 108
PCI 124
QDR
package length signal group 64
requirements 65
RSL requirements 35
U
Using x9 versus x18 QDR SRAM parts 58
V
Voltage, supply, power-up sequence 24
VREF generation, QDR SRAM 79
Index
153