Msf (Spi-4/Csix/Fc); Media And Switch Fabric Interface; Spi-4.2 - Intel IXP28XX Manual

MSF (SPI-4/CSIX/FC)

5.1
5.1.1
Hardware Design Guide
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Media and Switch Fabric Interface

The Media and Switch Fabric (MSF) Interface connects the Intel
Network Processor to a physical layer device (PHY) and/or a Switch Fabric Interface. The MSF
consists of the following external interfaces:
•
Receive and transmit interfaces, each of which can be individually configured for either the
SPI-4 Phase 2 (System Packet Interface) to a PHY or the CSIX-L1 protocol to a switch fabric.
•
A Flow Control Interface, which provides a point-to-point connection used primarily to pass
CSIX-L1 flow control C-Frames either between two network processors or between a network
processor and a switch fabric.
The MSF supports 16-bit DDR LVDS signaling for the SPI-4 data path channel and can be
configured to support either LVTTL or LVDS (Low-Voltage Differential Signal) signaling for the
SPI-4 FIFO status channel. The MSF supports 16-bit LVDS signaling for CSIX-L1 protocol and
4-bit LVDS signaling for the Flow Control interface.

SPI-4.2

SPI-4.2 is an interface for packet and cell transfer between a physical layer (PHY) device and a link
layer device (network processor) for aggregate bandwidths of OC-192 ATM and Packet over
SONET/SDH (POS), as well as 10 Gbyte/sec Ethernet applications.
The SPI-4.2 protocol transfers data in bursts of variable length. Associated with each burst is
information such as port number (for a multi-port device such as a 10 x 1 GbE), SOP, and EOP.
This information is collected by the MSF and passed to the Microengines.
The following implementations do not require an extra oscillator to provide a clock for the data that
moves between two network processors on the same line card:
•
The TD_CLK from network processor 1 to network processor 2 can be created by dividing
network processor 1's internal fast clock. The multiplex that selects between the two possible
sources of TD_CLK is controlled by a bit in the MSF_Tx_Control control status register
(CSR). This option is the more desirable of these implementations.
•
Optionally, the MAC device creates an RD_CLK to the first network processor, as shown in
Figure 58. RCLK_REF loops back into TCLK_REF for network processor 1 and TCLK_REF
is used as the source of the TD_CLK to network processor 2. Note that this implementation is
provided for documentation completeness; while it is feasible, it is not the more desirable
solution since the accumulated jitter from the source (MAC), PCB, and forwarding must be
accounted. The cumulative effect may result in the clock violating the duty cycle and/or
exceeding the jitter specification of the receiving device.
The Optical Internetworking Forum (OIF) controls the SPI-4.2 Implementation Agreement
document (available at http://www.oiforum.com).
IXP28XX Network Processor
MSF (SPI-4/CSIX/FC)
® ®
IXP2800 or Intel IXP2850
5
101