Slowport Mode 3 Write Example Showing Txe +1 Delay Using Sp_Txe - Intel IXP28XX Manual

Figure 86.
Example 4.
Hardware Design Guide
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Figure 86 is a Slowport Mode 3 Write example with TXE +1 delay using SP_TXE.

Slowport Mode 3 write example showing TXE +1 delay using SP_TXE

1 2 3 4 5
CPP_CLK 1
SP_CLK
1
SP_DIR 1
SP_ALE 1
SP_CS[1:0]
3
SP_WR 1
SP_AD[7:0] d8
SP_CP
0
SP_OE
0
SP_RD
1
SP_ACK
1
The Verilog* code in Example 4
32-bit Write Data Packing Logic Implementation
//implementation of latch control for 32-bit pack/unpacking to/from NP
//to uP port
always @(posedge sp_a[0]) begin
if (~rst_l) begin
data[31:0] <= 32'h0000_0000;
end
//data is shifted during four cycles
if (~sp_oe_l && sp_a[1]) begin
data[31:24] <= sp_ad_in;
data[23:16] <= data[31:24];
data[15:8] <= data[23:16];
data[7:0] <= data[15:8];
end
//here we can latch all the read data, the controller will
//pulse SPA[0] multiple times but it's a "don't care"
//as we capture all 32-bits on each edge of SP_CP
else begin
if (~sp_rd_l) begin
data[31:0]
end
end // else: !if(~sp_oe_l && sp_rd_l)
end // always @ (posedge spa[0])
In the Example 4 code, the 32-bit register used for latching the write data is also used for latching
the read data, decreasing the number of gates needed for implementing the glue logic. If desired,
separate registers for latching the write and read data can be used; in this case, the rising edge of the
SP_RD_L signal is used to capture the read data and the SP_CP signal is not used.
6 7 8 9 10 11 12 13 14 15 16
Internal bus clock
Rise of SP_CLK
3
d8
Rise of SP_CP
TXE+1 delay
is an example implementation of the logic.
<= uP_rd_data;
IXP28XX Network Processor
Slowport
17 18 19 20 21 22 23 24 25 26 27
7d
TXE in this run is 1 and delays
the change in data by
TXE+1 internal bus clocks
28
B3924-02
141