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IXP28XX Network Processor
Power Ratings and Requirements
2.5
Figure 6.
30
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IXP28XX Network Processor Power-On di/dt Profiles
Figure 6
illustrates IXP28XX network processor worst case power-up di/dt stimulus. The
characteristics of this transient event are as follows:
•
Reset leakage power is 3.68 W (2.7 A at 1.365 V).
•
Maximum power is 26.5 W.
•
After PLL locks the Microengine (1.4/1.0 GHz) the clock starts in 6 cycles as follows:
— Power ramps from leakage to approximately 49% of maximum power, or 12.985 W.
— The di/dt slope for step tr1 (see
over 6 cycles at a 1.4-GHz clock rate (1592 A per µs at VDD
•
Remaining clocks are started over 9 cycles as follows:
— Power ramps remaining rise to maximum power.
— The di/dt slope for step tr2 (see
step) over 9 cycles at a 1.4-GHz clock rate (1540 A per µs at VDD
•
Power decreases by 13.21 W to 13.28 W, approximately 67 REF_CLK cycles after PLL locks
in one cycle
— Sensitivity analysis shows that a duration of tr2 (see
second, or third droop.
IXP28XX Network Processor di/dt Stimulus
I
I
Intel
I_mid
tr1
I_lkg
6 tclks
4.28 ns
67 REF_CLK cycles or ~0.67 µs @ 100 MHz
Figure
6) represents a 9.29-W step (i.e., the transient step)
Figure
6) represents a 13.515-W step (i.e., the transient
®
IXP2800 Network Processor di/dt Stimulus
(B Step Power-Up Condition @ 1.365 V
with Microengine Reset)
Icc_max
tr2
tr3
9 tclks
1 tclk
6.43 ns
714 ps
).
MAX
).
MAX
Figure
6) does not affect the first,
I_final
Assumptions:
1. Reset Lkg power = 3.68 W
2. Enable only Microengine clock domain:
Power increase in one cycle (714 ps)
= 49% of total power or 3.68 W to
12.985 W = 9.29 W step.
3. Start Chassis and divided clock domains:
Remaining delta power increase,
13.515 W, to Icc_max in 9 cycles
or 6.4 ns.
4. Microengines come out of reset 1 µs
after PLL locks and power decreases by
13.21 W to 13.28 W.
t
B3556-01
Hardware Design Guide
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