Ixdp2800 Qdr Implementation Guidelines; Routing For A Four-Qdr Sram Topology; Qdr Sram Routing Recommendations - Intel IXP28XX Manual

IXP28XX Network Processor
QDR SRAM
4.8
Figure 47.
4.8.1
84
Downloaded from Elcodis.com electronic components distributor

IXDP2800 QDR Implementation Guidelines

The following is a list of QDR SRAM routing topologies that have been implemented on the
IXDP2800 Advanced Development Platform:
•
Simulation shows that no termination is required for two-device "clamshell" topology, as
shown in Figure 47.
•
Performance is at 250+ MHz.

QDR SRAM Routing Recommendations

Data, Controller,
SRAM Clks
®
Intel IXP2800
Network Processor
CIN[0]
* Note: Loopback clock length is determined from paper analysis. Actual implemented length may vary and
should be determined by performing a detailed timing analysis using extracted layout parasitics.

Routing for a Four-QDR SRAM Topology

For topologies using four loads during a read, only one SRAM drives the bus, and the stub to the
other SRAM causes a reflection that effectively reduces the data-valid window. The maximum
operating frequency is effectively, approximately 167 MHz.
The following are routing recommendations for four QDR SRAM topologies:
•
Only terminate lines on IXP28XX network processor drives.
•
OUTCLK/OUTCLK_L is 4.5 inches.
•
The x9 devices are recommended for topologies that use four loads, and for 200+ MHz
operations.
•
The x18 devices are recommended for 167+ MHz operations.
2.0" - 2.25"
Loopback Clock Length: 7.5"
C[1]
QDR
SRAM1
0.2" - 0.3"
0.2" - 0.3"
QDR
SRAM2
*
Hardware Design Guide
B3418-01